This invention pertains to integrated circuits and more specifically to the packaging of integrated circuits such that they may be electrically connected to other circuitry.
The fabrication of integrated circuits is a complex art. However, the art of packaging relatively fragile integrated circuit chips in order to protect them, provide electrical interconnection to other devices, and remove what often amounts to a significant quantity of heat, is also a very complex art. A continuing state of technological advancement in the packaging of integrated circuits has been necessary in order to keep up with the advances made in integrated circuit complexity, density, and speed. In addition, it is highly desirable to provide such state of the art integrated circuit packaging in a reliable low cost manner, while minimizing the yield loss encountered in the packaging process.
In addition to the need for packaging modern, high density integrated circuits having, in some cases, a large number of electrical pins, it has also become essential to be able to assemble a plurality of integrated circuit devices in a single electronic system or subsystem. Such systems or subsystems also require a low cost, reliable, high yield method for assembling a plurality of integrated circuit devices in a small area and in a manner such that a substantial amount of heat may be removed.
It is known, for example, to mount a plurality of integrated circuit dice on a substrate, such as a ceramic substrate or a printed circuit board, and provide wire interconnections from the dice to the substrate. The integrated circuit dice are then encapsulated, utilizing a suitable compound such as one of a variety of epoxies. It is also known in the prior art to provide electrical connection to an integrated circuit die utilizing tape automated bonding (TAB). The tape includes a predefined pattern of electrical traces including portions extending out into a window generally centrally located, which exposed leads are used for inner lead bonding (ILB) to raised metallic bumps formed on the bonding pads of the integrated circuit die or on the tape. The traces on the tape extend to an outer edge where they are exposed for the purposes of outer lead bonding (OLB) to a lead frame, which is then encapsulated with a suitable epoxy in order to form a dual in line package (DIP) including package leads for electrical connection to other circuitry. For higher density application, packages have been developed which include more than one row of leads associated with each edge of the package. Surface mount devices (SMD) have been developed which either include small leads, or which are leadless, and which are designed for mounting on the surface of a printed circuit board without requiring a through hole formed in the printed circuit board. In yet another approach, the TAB outer lead bonding is made directly to a printed circuit board.
A good description of a wide variety of packaging techniques is provided in "Microelectronics Packaging Handbook," edited by R. Tummala & E. Rymaszewski, Van Nostrand Reinhold (1989), New York.
Another technique for packaging integrated circuits is described in U.S. Pat. No. 4,426,689 issued Jan. 17, 1984, to Henle et. al. Henle et. al. describe the assembly of integrated circuit dice by vertically mounting them on a horizontal substrate. Henle et. al. describe a first embodiment where all bonding pads on an integrated circuit die are located along one edge such that appropriate bonding techniques can be used to electrically and physically connect the integrated circuit bonding pads to corresponding electrical connection regions on the surface of the substrate. This allows a plurality of integrated circuit dice to be vertically mounted on a horizontal substrate in close proximity, thereby providing high packaging density.
Henle et. al. also describes the use of TAB for assembling the plurality of dice to the substrate. Henle et. al. describes TAB mounting a plurality of dice, which may have their bonding pads located along more than one edge. In this embodiment of Henle et. al., each die is mounted by inner lead bonding bumps formed on the bonding pads of the die to metallic fingers which extend into a window region of the tape, such that the dice are suspended within their associated windows. Henle et. al. then bend the tape in order to form a convoluted tape structure having dice suspended in the windows in a vertical fashion with respect to the horizontal substrate. Portions of the convoluted tape structure which do not contain the integrated circuit dice are formed substantially parallel to the surface of the substrate to allow outer lead bonding of the convoluted tape structure to appropriate metallic interconnects located on the surface of the substrate. Henle et. al. describe that the portions of the metallic traces on the tape which are to be used for outer lead bonding are formed in an open window, i.e. they extend into the window devoid of tape.
Henle et. al. describe the formation of a right angle connector for use in the first embodiment of their invention which does not utilize TAB. Henle et. al. describe that a metallic connector is bonded to the bonding pads and then clamped in a suitable tool. The integrated circuit die is then rotated with respect to the clamping device thereby causing the leads to be bent. This technique is also apparently used by Henle et. al. for causing the tape used in the second embodiment of Henle et. al. to be formed in a convoluted structure, i.e. clamping the portions of the tape which are to be outer lead bonded to the substrate, and which holds an integrated circuit die rotated with respect to the clamped portion of the tape.
Thus, Henle et. al. describe a TAB packaging technique in which a plurality of integrated circuit dice are inner lead bonded on a single piece of tape, which is then convoluted and outer lead bonded to a substrate, thereby connecting a plurality of integrated circuit dice to the substrate as one unit.
It is therefore one objective of this invention to provide a semiconductor package with increased interconnect density.
It is another objective of the present invention to provide a semiconductor package with increased yield, by allowing testing of individual components prior to assembly, and a reworking of the device by the replacement of individual assemblies, if needed.